Advances this decade in silicon technology have enabled design engineers to examine new methods of generating circuit designs. One such method has become known, which considers the automated design of digital systems using both software simulation and programmable hardware technologies. Automated circuit design attempts to redefine the methodology by which electrical circuits are developed. Traditional techniques utilize a top down or compartmentalized design methodology by which complex systems are broken down into small sub-systems and assigned to a number of design groups. A distinct feature of the algorithm is its ability to directly evolve and evaluate circuits in a VHDL (Very High Speed Integrated Hardware Description Language, within a environment termed the Virtual Chip. Because the Virtual Chip evolves circuit structures within a VHDL, detailed simulation and analysis of each circuit is possible with any technology specific component library. This feature allows accurate analysis of performance issues such as timing and area. The paper describes the genetic algorithm and the hardware evaluation environment, and provides results with a number of benchmark arithmetic circuits evolved under different performance driven timing and area constraints. Our study reveal that the genetic algorithm is able to exploit the flexibility provided by a novel chromo some architecture, and utilize a combination of primitive gates and macro components from a component library, in order to produce circuits which operate well within timing restrictions.

Author Name: Rajeev Saraswat, Prashant Sen

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Keywords: Digital Circuits, Genetic Algorithms,VHDL

ISSN: 2455-6203

EISSN: 2455-6203

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