Today, every SSI and MSI function can be implemented with a CPLD (Complex Programmable Logic Device) using the
VHDL codes. The design starts with entry through the VHDL code. The program is saved in the .svf file. For implementation
of the digital circuit, the program is transferred to the CPLD via JTAG USB cable, using the ISP technique.
This paper presents the technique of preparing the VHDL code for an 8-bit Sequence detector and a Mod-10 ripple counter
circuits. The circuits have been successfully implemented with the CPLD chip and the simulation waveforms are obtained.
Real Time Impact Factor:
Pending
Author Name: Miss. Priyanka D. Ambagade1, Prof.M S. Korde2
URL: View PDF
Keywords: Keywords: Quartus II, Altera, Altera Simulator, JTAG
ISSN: 2348-0831
EISSN: 2348-0831
EOI/DOI:
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