Initially SEA is designed for software implementations in controllers, smart cards, or processors. In this
Paper we proposed a system that investigates its performances in recent field-programmable gate array (FPGA) devices. The present symmetric encryption algorithms result from a tradeoff between implementation cost
and resulting performances. The proposed system is applicable where there are limited processing resources with high
throughput requirements. For this purpose, we propose a SEA loop Architecture with Behavior model (VerlogHDL) coding. So the number of logic gates required is very less when compared with Gate level model. Because of less number
of logic gates, time taken to execute the loop architecture is less. So we are achieving a faster execution time (Frquency in MHZ). The proposed design is parametric in the key and word size, provably secure against linear or differential cryptanalysis. Beyond its low cost performances, a significant advantage of the proposed architecture is its full
flexibility for any parameter of the scalable encryption algorithm, taking advantage of generic VerlogHDL coding with
Xilinx Spartan 3 - 3s400ft256-5
Real Time Impact Factor:
Pending
Author Name: Mr.K.ASHOKKUMAR, Mr.G.SENTHILKUMAR, Mrs.S. POONGUZHALI
URL: View PDF
Keywords: FPGA – Field Programmable Gate Array, Computer security, DES - Data Encryption Standard, Verilog HDL.
ISSN: 2249-555X
EISSN: 2249-555X
EOI/DOI: 10.15373/2249555X
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