This work presents the design of a current mode class-D (CMCD) amplifier using simulation. Two separate designs are considered for simulation by using LDMOS FET and BJT with frequency range 1GHz to 3GHz. The CMCD architecture is an improvement over the Voltage Mode Class-D (VMCD) in that the parasitic reactance in the active device can be absorbed into the tank circuit resulting in a zero voltage switching condition. This amplifier has achieved a PAE of 54.08% with an output power of 39.29dBm (8.5W) and a gain of 9.94 dB at 2.6GHz with BJT. The simulation result of BJT shows high efficiency and higher bandwidth than LDMOS FET.
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Author Name: Mohammed Jashim Uddin, Syed Zahidur Rashid
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Keywords: IJSER,2229-5518,22295518,Mohammed Jashim Uddin, Syed Zahidur Rashid